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File name   :  vv_ahblite_config.e
Title       :  Configuration file
Project     :  vv_ahblite UVC
Developers  :  stefan, filip
Created     :  Fri Jul  8 11:54:04 2011
Description :  This file configures the UVC.
Notes       :  
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Copyright  (c)2011
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-- Defines

-- Import the vv_ahblite UVC
import vv_ahblite/e/vv_ahblite_top;

-- *************************************************************************
-- IVB-NOTE : REQUIRED : Instantiating UVCs : 08 Example - configuration
-- -------------------------------------------------------------------------
-- Use this section to instantiate all the UVC instances used.
-- To do so edit the following example, which adds one instance of the UVC:

-- Step 1 - Create a logical name for each UVC instance. 
extend vv_ahblite_env_name_t : [ENV_0];

-- Step 2 - Instantiate the UVCs under sys.
--          Where there is more than one instance you can either have
--          multiple instances or create a list of instances.
extend sys {
    
   vv_ahblite_evc : ENV_0 vv_ahblite_env is instance;
      keep vv_ahblite_evc.hdl_path() == "vv_ahblite_skeleton";
    
};

-- *************************************************************************



-- *************************************************************************
-- IVB-NOTE : REQUIRED : Operation modes : 08 Example - configuration
-- -------------------------------------------------------------------------
-- Use this section to set the modes of operation of each UVC instance.
-- To do so edit the following example:

extend ENV_0 vv_ahblite_env {
    
    -- The master agent is called M0 and is active
    keep master is a M0 ACTIVE vv_ahblite_master;
    
    -- This instanciate the slave agents
    keep passive_slave_names  == {};
    keep active_slave_names     == {S0; S1};
    
    -- This instance of the UVC has coverage collection
    keep has_coverage == TRUE;
    -- This instance of the UVC has a protocol checker
    keep has_checks == TRUE;
    
    post_generate() is also {
        for each (s) in slaves {
            addr_map.add_with_offset(s.min_addr,s.mem);
        }; 
    };
   
}; 

-- *************************************************************************


-- Signal map configuration
-- Configure the UVC instance. This section sets up how the UVC accesses
-- DUT signals.
extend ENV_0 vv_ahblite_smp {
    
    -- **********************************************************************
    -- IVB-NOTE : REQUIRED : Signal names : 08 Example - configuration
    -- ----------------------------------------------------------------------
    -- Use this section to bind the UVC's ports to the DUT signals, by
    -- setting the right HDL path.
    -- To do so edit the following example:
	
	 -- activate the default slave behaviore
    keep  has_default_slave == TRUE;
    
    -----DEFAULT SLAVE INIT ---
    keep AHB_HRESP == read_only(h_resp_S3);
    keep AHB_HREADY == read_only(h_readyout_S3);
    keep AHB_HRDATA == read_only(h_rdata_S3);
    keep AHB_DEFAULT_SLAVE_HSEL == read_only(h_sel_s3);
    -------------------------------------------------------
	
	
    keep h_addr.hdl_path()      == "h_addr";
    keep h_addr.verilog_wire()  == TRUE;
    keep h_addr.declared_range() == "[31:0]";
    
    keep h_write.hdl_path()     == "h_write";
    keep h_write.verilog_wire() == TRUE;
    
    keep h_size.hdl_path()     == "h_size";
    keep h_size.verilog_wire() == TRUE;
    keep h_size.declared_range() == "[2:0]";
    
    keep h_burst.hdl_path()     == "h_burst";
    keep h_burst.verilog_wire() == TRUE;
    keep h_burst.declared_range() == "[2:0]";
    
    keep h_prot.hdl_path()     == "h_prot";
    keep h_prot.verilog_wire() == TRUE;
    keep h_prot.declared_range() == "[3:0]";

    keep h_trans.hdl_path()     == "h_trans";
    keep h_trans.verilog_wire() == TRUE;
    keep h_trans.declared_range() == "[1:0]";
    
    keep h_mastlock.hdl_path()     == "h_mastlock";
    keep h_mastlock.verilog_wire() == TRUE;
    
    keep h_wdata.hdl_path()     == "h_wdata";
    keep h_wdata.verilog_wire() == TRUE;
    keep h_wdata.declared_range() == "[31:0]";
    
    keep h_ready.hdl_path()     == "h_ready";
    keep h_ready.verilog_wire() == TRUE;
    
    keep h_resp.hdl_path()     == "h_resp";
    keep h_resp.verilog_wire() == TRUE;
    
    keep h_rdata.hdl_path()     == "h_rdata";
    keep h_rdata.verilog_wire() == TRUE;
    keep h_rdata.declared_range() == "[31:0]";
    
    -- HSELx
    keep h_sel_s0.hdl_path()     == "h_sel_s0";
    keep h_sel_s0.verilog_wire() == TRUE;
    
    keep h_sel_s1.hdl_path()     == "h_sel_s1";
    keep h_sel_s1.verilog_wire() == TRUE;
    
    keep h_sel_s2.hdl_path()     == "h_sel_s2";
    keep h_sel_s2.verilog_wire() == TRUE;
    
    keep h_sel_s3.hdl_path()     == "h_sel_s3";
    keep h_sel_s3.verilog_wire() == TRUE;
    
    -- signals for SLAVE 0
    
    keep h_rdata_S0.hdl_path()     == "h_rdata_S0";
    keep h_rdata_S0.verilog_wire() == TRUE;
    keep h_rdata_S0.declared_range() == "[31:0]";
    
    keep h_resp_S0.hdl_path()     == "h_resp_S0";
    keep h_resp_S0.verilog_wire() == TRUE;
    
    keep h_readyout_S0.hdl_path()     == "h_readyout_S0";
    keep h_readyout_S0.verilog_wire() == TRUE;    
    
        -- signals for SLAVE 1
    
    keep h_rdata_S1.hdl_path()     == "h_rdata_S1";
    keep h_rdata_S1.verilog_wire() == TRUE;
    keep h_rdata_S1.declared_range() == "[31:0]";
    
    keep h_resp_S1.hdl_path()     == "h_resp_S1";
    keep h_resp_S1.verilog_wire() == TRUE;
    
    keep h_readyout_S1.hdl_path()     == "h_readyout_S1";
    keep h_readyout_S1.verilog_wire() == TRUE;
    
        -- signals for SLAVE 2
    
    keep h_rdata_S2.hdl_path()     == "h_rdata_S2";
    keep h_rdata_S2.verilog_wire() == TRUE;
    keep h_rdata_S2.declared_range() == "[31:0]";
    
    keep h_resp_S2.hdl_path()     == "h_resp_S2";
    keep h_resp_S2.verilog_wire() == TRUE;
    
    keep h_readyout_S2.hdl_path()     == "h_readyout_S2";
    keep h_readyout_S2.verilog_wire() == TRUE;    
    
        -- signals for SLAVE 3
    
    keep h_rdata_S3.hdl_path()     == "h_rdata_S3";
    keep h_rdata_S3.verilog_wire() == TRUE;
    keep h_rdata_S3.declared_range() == "[31:0]";
    
    keep h_resp_S3.hdl_path()     == "h_resp_S3";
    keep h_resp_S3.verilog_wire() == TRUE;
    
    keep h_readyout_S3.hdl_path()     == "h_readyout_S3";
    keep h_readyout_S3.verilog_wire() == TRUE;    
    
    -- **********************************************************************
    
}; 

-- *************************************************************************
-- IVB-NOTE : REQUIRED : Configure UVC master : 08 Example - configuration
-- -------------------------------------------------------------------------
-- Use this section to configure the UVC master agent.
-- To do so edit the following example:
-- Configure M0
extend ENV_0 M0 vv_ahblite_master {
	
	-- This agent has coverage collection
    keep has_coverage == TRUE;
    -- This agent has a protocol checker
    keep has_checks == TRUE;
    
};
-- *************************************************************************
-- IVB-NOTE : REQUIRED : Configure UVC slaves : 08 Example - configuration
-- -------------------------------------------------------------------------
-- Use this section to configure the UVC slaves.
-- This action should be done for each one of the slave instances.
-- To do so edit the following example:

-- Configure S0
extend ENV_0 S0 vv_ahblite_slave {
	
	-- This agent has coverage collection
    keep has_coverage == TRUE;
    -- This agent has a protocol checker
    keep has_checks == TRUE;
	
    -- Set the slave memory size
    keep mem.size == (max_addr - min_addr);
    
    -- This slave responds to address in the range 
    keep min_addr == 0;
    keep max_addr == 32767;
    
    -- connect ports with signals in design
    keep h_sel == read_only(p_smp.h_sel_s0);
    keep h_readyout == read_only(p_smp.h_readyout_S0);
    keep h_resp == read_only(p_smp.h_resp_S0);
    keep h_rdata == read_only(p_smp.h_rdata_S0);
    
    keep use_mem == TRUE;
};

-- Configure S1
extend ENV_0 S1 vv_ahblite_slave {
	
	-- This agent has coverage collection
    keep has_coverage == TRUE;
    -- This agent has a protocol checker
    keep has_checks == TRUE;
    
    -- Set the slave memory size
    keep mem.size == (max_addr - min_addr);
    
    -- This slave responds to address in the range 
    keep min_addr == 32768;
    keep max_addr == 65535;
    
    -- connect ports with signals in design
    keep h_sel == read_only(p_smp.h_sel_s1);
    keep h_readyout == read_only(p_smp.h_readyout_S1);
    keep h_resp == read_only(p_smp.h_resp_S1);
    keep h_rdata == read_only(p_smp.h_rdata_S1);
    
    keep use_mem == TRUE;
};

-- *************************************************************************
      

extend ENV_0 vv_ahblite_system_smp {
     
    -- **********************************************************************
    -- IVB-NOTE : REQUIRED : System signal names : 08 Example - configuration
    -- ----------------------------------------------------------------------
    -- Use this section to bind the system ports to the system DUT signals,
    -- by setting the right HDL path.
    -- To do so edit the following example:
    
    keep clk.hdl_path()      == "clock";
    
    keep resetn.hdl_path()     == "reset_n";
        
    -- **********************************************************************
};

extend sys {
    setup() is also {
        
        -- ******************************************************************
        -- IVB-NOTE : OPTIONAL : Specman Environment : 08 Example - configuration
        -- ------------------------------------------------------------------
        -- Use this section to change the default Specman configuration
        -- options. To do so edit the following example:
        
        set_config(print, radix, hex);
        set_config(run, tick_max, 10000000);
        
        -- ******************************************************************
    };
};


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